In order to fabricate high performance interconnect structures for state of the art semiconductor devices, it is necessary to embed a conductive material such as Cu into a dielectric material having a trench or via formed therein. Organic as well as inorganic dielectric materials are known and are currently being employed in such applications. Examples of organic dielectrics include: polyimides, paralyne polymers, silicon polymers, i.e. polysiloxanes, diamond, diamond-like carbon and the like, while SiO2, Si3N4, silicon oxide/nitride mixtures or alternating oxide/nitride layers are known inorganic dielectrics.
While Cu is currently being developed for use in semiconductor manufacturing by the assignee herein for such applications, it exhibits a number of undesirable properties. One highly undesirable property that Cu exhibits is that it generally diffuses through the dielectric material at the moderately elevated temperatures encountered during subsequent processing steps. The out-diffusion of Cu can have a number of deleterious effects on the interconnect structure being manufactured. For example, the out-diffusion of Cu may cause short circuiting of the wires or it may degrade the performance of the MOS device.
To overcome this out-diffusion problem exhibited by Cu, a barrier layer is generally formed between Cu and the dielectric material. In prior instances, the material used in forming the barrier layer has not been compatible with the dielectric material, i.e. it does not adhere well to the dielectric material. Thus, an additional adhesion layer has been required in order to achieve satisfactory adhesion of the barrier layer material to the dielectric.
A typical prior art interconnect structure containing a dielectric, an additional adhesion layer, a barrier layer and Cu is shown in FIG. 1. Specifically, this prior art interconnect structure shown in FIG. 1 comprises a dielectric 10 having at least one trench or via formed therein, an adhesion layer 12, a barrier layer 14 and Cu region 16. The trench or via is formed in the surface of dielectric 10 using standard lithographic patterning techniques that are well known to those skilled in the art. It should be emphasized that although the various layers are shown as conformal layers in FIG. 1 in reality the layers are non-conformal since the previous prior art processing techniques used in forming the various layers are incapable of providing conformal trench coverage.
As stated above, the adhesion layer is only required when barrier layer 14 is not compatible with dielectric 10. Suitable materials for the adhesion layer include: Ti, Cr and other similar materials. The adhesion layer is formed using standard deposition techniques such as sputtering. The Cu region is formed using plating, chemical vapor deposition, plasma vapor deposition and like techniques which are also well known in the art.
The barrier layer in the prior art structure of FIG. 1 is typically composed of a metal such as Ta. The prior art barrier layers may be formed using sputtering and other known deposition techniques.
Although a wide range of materials can be employed as barrier layer 14, the prior art barrier layers do not meet all of the following requirements which are now deemed as necessary in the fabrication of interconnect structures:    (1). The barrier layer must be impermeable to Cu under the conditions to which the device will experience in further processing, as well as under operating conditions;    (2). The barrier layer must exhibit good adhesion to the dielectric comprising the interconnect structure; therefore, obviating the need for an additional adhesion layer;    (3). The barrier layer must be formed in such a manner as to comformally and continuously cover a high aspect ratio trench. By “high aspect ratio”, it is meant a trench wherein the depth to width ratio is greater than 3:1;    (4). The barrier layer should be as thin as possible, so as to maximize the fraction of the cross-section of the trench which may be filled with the Cu wiring, so as to maximize wire conductivity;    (5). The barrier layer should be of uniform thickness throughout the structure, i.e. coverage of the interconnect trench should be conformal. A barrier failure will be determined by the thinnest region of the structure, non-uniformity in thickness will necessarily be wasteful of the trench cross-sectional area;    (6). The barrier layer should be made from a material that has the lowest possible resistivity so as to aide in minimizing the total wire resistivity; and    (7). The barrier layer should be resistant to oxidation so as to facilitate the filling of the remaining trench volume with Cu with a minimum of pretreatment steps or processes.
While prior art barrier layers may satisfy one or more of the above criteria, none of the barrier layers provided in prior art processes are known to satisfy all of them. Thus, there is a need to develop a new barrier layer that satisfies each and every criteria mentioned hereinabove. Such a barrier layer would be extremely useful in all semiconductor interconnect applications wherein Cu or another conductive metal is found.